`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date: 2021/07/05 18:24:59
// Design Name: 
// Module Name: latch
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


/*
    general m-bit latch with enable & async clear
*/
module latch(din, clk, en, clr, dout);
    parameter m = 8;
    
    input [m-1:0] din;
    input clk, en, clr;
    output [m-1:0] dout;
    reg [m-1:0] o;
    
    initial o = 3;

    always @(posedge clk, posedge clr)
    begin
        if(clr)
            o <= 0;
        else if(en)
            o <= din;
    end
    assign dout = o;
endmodule